? semiconductor components industries, llc, 2005 december, 2005 ? rev. 2 1 publication order number: MCR68/d MCR68?2 silicon controlled rectifiers reverse blocking thyristors designed for overvoltage prot ection in crowbar circuits. features ? glass-passivated junctions for greater parameter stability and reliability ? center-gate geometry for uniform current spreading enabling high discharge current ? small rugged, thermowatt package constructed for low thermal resistance and maximum power dissipation and durability ? high capacitor discharge current, 300 amps ? pb?free package is available* maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit peak repetitive off?state voltage (note 1) (t j = 40 to +125 c, gate open) MCR68?2 v drm, v rrm 50 v peak discharge current (note 2) i tm 300 a on-state rms current (180 conduction angles; t c = 85 c) i t(rms) 12 a average on-state current (180 conduction angles; t c = 85 c) i t(av) 8.0 a peak non-repetitive surge current (1/2 cycle, sine wave, 60 hz, t j = 125 c) i tsm 100 a circuit fusing considerations (t = 8.3 ms) i 2 t 40 a 2 s forward peak gate current (t 1.0 s, t c = 85 c) i gm 2.0 a forward peak gate power (t 1.0 s, t c = 85 c) p gm 20 w forward average gate power (t = 8.3 ms, t c = 85 c) p g(av) 0.5 w operating junction temperature range t j ?40 to +125 c storage temperature range t stg ?40 to +150 c mounting torque ? 8.0 in. lb. maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. v drm and v rrm for all types can be applied on a continuous basis. ratings apply for zero or negative gate voltage; however, positive gate voltage shall not be applied concurrent with negative potential on the anode. blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. 2. ratings apply for t w = 1 ms. see figure 1 for i tm capability for various duration of an exponentially decaying current waveform, t w is defined as 5 time constants of an exponentially decaying current pulse. *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. scrs 12 amperes rms 50 volts to?220ab case 221a?07 style 3 1 http://onsemi.com ay ww MCR68?2g aka marking diagram a = assembly location y = year ww = work week g = pb?free package aka = diode polarity 2 3 preferred devices are recommended choices for future use and best overall value. device package shipping ordering information MCR68?2 to?220ab 500 units / box MCR68?2g to?220ab (pb?free) 500 units / box k g a pin assignment 1 2 3 anode gate cathode 4 anode
MCR68?2 http://onsemi.com 2 thermal characteristics characteristic symbol max unit thermal resistance, junction?to?case r jc 2.0 c/w thermal resistance, junction?to?ambient r ja 60 c/w maximum lead temperature for soldering purposes 1/8 from case for 10 seconds t l 260 c electrical characteristics (t c = 25 c unless otherwise noted.) characteristic symbol min typ max unit off characteristics peak repetitive forward or reverse blocking current (v ak = rated v drm or v rrm , gate open) t j = 25 c t j = 125 c i drm , i rrm ? ? ? ? 10 2.0 a ma on characteristics peak forward on-state voltage (i tm = 24 a) (note 3) (i tm = 300 a, t w = 1 ms) (note 4) v tm ? ? ? 6.0 2.2 ? v gate trigger current (continuous dc) (v d = 12 v, r l = 100 ) i gt 2.0 7.0 30 ma gate trigger voltage (continuous dc) (v d = 12 v, r l = 100 ) v gt ? 0.65 1.5 v gate non?trigger voltage (v d = 12 vdc, r l = 100 , t j = 125 c) v gd 0.2 0.40 ? v holding current (v d = 12 v, initiating current = 200 ma, gate open) i h 3.0 15 50 ma latching current (v d = 12 vdc, i g = 150 ma) i l ? ? 60 ma gate controlled turn-on time (note 5) (v d = rated v drm , i g = 150 ma) (i tm = 24 a peak) t gt ? 1.0 ? s dynamic characteristics critical rate-of-rise of off-state voltage (v d = rated v drm , gate open, exponential waveform, t j = 125 c) dv/dt 10 ? ? v/ s critical rate-of-rise of on-state current i g = 150 ma t j = 125 c di/dt ? ? 75 a/ s 3. pulse duration 300 s, duty cycle 2%. 4. ratings apply for t w = 1 ms. see figure 1 for i tm capability for various durations of an exponentially decaying current waveform. t w is defined as 5 time constants of an exponentially decaying current pulse. 5. the gate controlled turn-on time in a crowbar circuit will be influenced by the circuit inductance.
MCR68?2 http://onsemi.com 3 + current + voltage v tm i drm at v drm i h symbol parameter v drm peak repetitive off state forward voltage i drm peak forward blocking current v rrm peak repetitive off state reverse voltage i rrm peak reverse blocking current v tm peak on state voltage i h holding current voltage current characteristic of scr anode + on state reverse blocking region (off state) reverse avalanche region anode ? forward blocking region i rrm at v rrm (off state) i , peak discharge current (amps) tm normalized peak current 300 20 50 100 200 20 1000 0.5 50 t w , pulse current duration (ms) 2.0 1.0 t w t w = 5 time constants i tm 10 5.0 0.8 25 0 0.2 0.4 0.6 1.0 50 75 100 125 t c , case temperature ( c) figure 1. peak capacitor discharge current figure 2. peak capacitor discharge current derating t , maximum c case temperature ( c) 75 80 85 90 95 100 105 110 115 120 125 5.0 2.0 1.0 8.0 10 i t(av) , average on-state current (amps) dc half wave figure 3. current derating p , average power dissipation (watts) (av) 2.0 4.0 8.0 10 14 18 20 half wave dc 5.0 2.0 1.0 8.0 10 4.0 i t(av) , average on-state current (amps) t j = 125 c figure 4. maximum power dissipation
MCR68?2 http://onsemi.com 4 2 k 10 k 5 k 3 k 10 t, time (ms) 1 k 500 300 200 100 50 30 0.2 20 1 0.7 0.5 0.1 0.2 0.02 5 23 1 0.5 0.3 0.1 0.3 0.07 0.05 0.03 0.01 z jc(t) = r jc ? r(t) r(t), transient thermal resistance(normalized) figure 5. thermal response normalized gate trigger current normalized gate trigger voltage normalized hold current ?40 10 0.2 0.3 140 120 100 80 60 40 ?20 0 20 0.5 1.2 1.0 0.8 ?40 ?60 1.4 t j , junction temperature ( c) 40 020 60 0.5 3.0 5.0 140 80 100 120 2.0 1.0 ?20 ?60 t j , junction temperature ( c) v d = 12 volts r l = 100 v d = 12 volts r l = 100 0.3 0.5 0.8 1.0 140 120 40 100 3.0 2.0 20 60 80 0 ?40 t j , junction temperature ( c) ?20 ?60 v d = 12 volts i tm = 100 ma figure 6. gate trigger current figure 7. gate trigger voltage figure 8. holding current
MCR68?2 http://onsemi.com 5 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension z defines a zone where all body and lead irregularities are allowed. style 3: pin 1. cathode 2. anode 3. gate 4. anode dim min max min max millimeters inches a 0.570 0.620 14.48 15.75 b 0.380 0.405 9.66 10.28 c 0.160 0.190 4.07 4.82 d 0.025 0.035 0.64 0.88 f 0.142 0.147 3.61 3.73 g 0.095 0.105 2.42 2.66 h 0.110 0.155 2.80 3.93 j 0.014 0.022 0.36 0.55 k 0.500 0.562 12.70 14.27 l 0.045 0.060 1.15 1.52 n 0.190 0.210 4.83 5.33 q 0.100 0.120 2.54 3.04 r 0.080 0.110 2.04 2.79 s 0.045 0.055 1.15 1.39 t 0.235 0.255 5.97 6.47 u 0.000 0.050 0.00 1.27 v 0.045 ??? 1.15 ??? z ??? 0.080 ??? 2.04 a k l v g d n z h q f b 123 4 ?t? seating plane s r j u t c to?220ab case 221a?07 issue aa on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 MCR68/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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